BIT b,(IY+d)

Operation

     _______
Z <- (IY+d)b

Mnemonic

BIT

Operands

b,(IY+d)

b7b6b5b4b3b2b1b0
1 1 1 1 1 1 0 1$FD
1 1 0 0 1 0 1 1$CB
d
0 1 b 1 1 0

Description

This instruction tests bit b in the memory location specified by the contents of register pair IY combined with the two’s complement displacement d and sets the Z flag accordingly. In the assembled object code, operand b is specified as follows:

Bit TestedHex
0000$46
1001$4E
2010$56
3011$5E
4100$66
5101$6E
6110$76
7111$7E

Condition Bits Affected

Sis unknown.
Zis set if specified bit is 0, otherwise it is reset.
His set.
P/Vis unknown
Nis reset.
Cis not affected.

Example

If Index Register IY contains $2000 and bit 6 in memory location $2004 contains 1, then upon the execution of

	BIT	6,(IY+$4)

the Z flag in the F Register contains a 0 and bit 6 in memory location $2004 still contains a 1. Bit 0 in memory location $2004 is the least-significant bit.