SRL (IY+d)

Operation

     n----------m  n--m
0 -->|7------->0|->|CY|
     v----------u  v--u
        (IY+d)

Mnemonic

SRL

Operands

(IY+d)

b7b6b5b4b3b2b1b0
1 1 1 1 1 1 0 1$FD
1 1 0 0 1 0 1 1$CB
d
0 0 1 1 1 1 1 0$3E

Description

The contents of the memory address specified by the sum of the contents of Index Register IY and the two's-complement displacement integer, d, are shifted right 1 bit posistion. The contents of bit 0 are copied to the Carry flag, and bit 7 is reset.

Condition Bits Affected

Sis set reset.
Zis set if result is 0, otherwise it is reset.
His reset.
P/Vis set if parity even, otherwise it is reset
Nis reset.
Cis data from bit 0.

Example

Index Register IY contains $1000 and the contents of memory location $1002 are:

76543210
10001111

Upon the execution of

	SRL	(IY+$2)

memory location $1002 and the Carry flag now contain:

76543210C
010001111