|
| Interrups | Categories | Contents |
Notes: Intel documents this interrupt as CPU model-dependent. For current Pentium processors, the reason for the machine check exception may be read from model-specific registers 00h and 01h (described, for example, in Christian Ludloff's 4P package). For Pentium Pro/II processors, the reason may be read from the MCG_STATUS MSR (see MSR 0000017Ah). This exception is enabled by bit 6 of CR4
See Also: INT 11"CPU" - MSR 00000000h - MSR 00000001h - MSR 0000017Ah
Category: CPU-Generated - Int 12h - C
|
| Interrups | Categories | Contents |