ADC HL,ss

Operation

HL <- HL + ss + CY

Mnemonic

ADC

Operands

HL,ss

b7b6b5b4b3b2b1b0
1 1 1 0 1 1 0 1$ED
0 1 ss 1010

Description

The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added with the Carry flag (C flag in the F Register) to the contents of register pair HL, and the result is stored in HL. In the assembled object code, operand ss is specified as follows:

Register
Pair
rHex
BC00$4A
DE01$5A
HL10$6A
SP11$7A

Condition Bits Affected

Sis set if result is negative, otherwise it is reset.
Zis set if result is 0, otherwise it is reset.
His set if carry from bit 11, otherwise it is reset.
P/Vis set if overflow, otherise it is reset.
Nis reset.
Cis set if carry from bit 15, otherwise it is reset.

Example

If register pair BC contains $2222, register pair HL contains $5437, and the Carry Flag is set, then upon the execution of

	ADC	HL,BC

the HL register pair contains $765A.