_______ Z <- (IX+d)b
BIT
b,(IX+d)
| b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | $DD |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | $CB |
| d | ||||||||
| 0 | 1 | b | 1 | 1 | 0 | |||
This instruction tests bit b in the memory location specified by the contents of register pair IX combined with the two’s complement displacement d and sets the Z flag accordingly. In the assembled object code, operand b is specified as follows:
| Bit Tested | Hex | |
|---|---|---|
| 0 | 000 | $46 |
| 1 | 001 | $4E |
| 2 | 010 | $56 |
| 3 | 011 | $5E |
| 4 | 100 | $66 |
| 5 | 101 | $6E |
| 6 | 110 | $76 |
| 7 | 111 | $7E |
| S | is unknown. |
| Z | is set if specified bit is 0, otherwise it is reset. |
| H | is set. |
| P/V | is unknown |
| N | is reset. |
| C | is not affected. |
If Index Register IX contains $2000 and bit 6 in memory location $2004 contains 1, then upon the execution of
BIT 6,(IX+$4)
the Z flag in the F Register contains a 0 and bit 6 in memory location $2004 still contains a 1. Bit 0 in memory location $2004 is the least-significant bit.