A - (HL), HL <- HL-1, BC <- BC-1
CPDR
None
| b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | $ED |
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | $B9 |
The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. During a compare operation, a condition bit is set. The HL and Byte Counter (BC) Register pairs are decremented. If decrementing allows the BC to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A = (HL), the program counter is decremented by two and the instruction is repeated. Interrupts are recognized and two refresh cycles execute after each data transfer.
If BC is set to 0 before instruction execution, the instruction loops through 64 KB if no match is found.
| S | is set if result is negative, otherwise it is reset. |
| Z | is set if A equal (HL), otherwise it is reset. |
| H | is set if borrow from bit 4, otherwise it is reset. |
| P/V | is set if BC-1 does not equal 0, otherwise it is reset. |
| N | is set. |
| C | is not affected. |
The HL register pair contains $1118, the Accumulator contains $F3, the Byte Counter contains $0007, and memory locations contain the following data.
| ($1118) | contains | $52 |
| ($1117) | contains | $00 |
| ($1116) | contains | $F3 |
Upon the execution of
CPDR
register pair HL contains $1115, the Byte Counter contains $0004, the P/V flag in the F Register is set, and the Z flag in the F Register is set.