A - (HL), HL <- HL+1, BC <- BC-1





1 1 1 0 1 1 0 1$ED
1 0 1 1 0 0 0 1$B1


The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. During a compare operation, a condition bit is set. HL is incremented and the Byte Counter (register pair BC) is decremented. If decrementing causes BC to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A != (HL), the program counter is decremented by two and the instruction is repeated. Interrupts are recognized and two refresh cycles are executed after each data transfer.

If BC is set to 0 before instruction execution, the instruction loops through 64 KB if no match is found.

Condition Bits Affected

Sis set if result is negative, otherwise it is reset.
Zis set if A equal (HL), otherwise it is reset.
His set if borrow from bit 4, otherwise it is reset.
P/Vis set if BC-1 does not equal 0, otherwise it is reset.
Nis set.
Cis not affected.


If the HL register pair contains $1111, the Accumulator contains $F3, the Byte Counter contains $0007, and memory locations contain the following data.


Upon the execution of


register pair HL contains $1114, the Byte Counter contains $0004, the P/V flag in the F Register is set, and the Z flag in the F Register is set.