(HL) <- (C), B <- B-1, HL <- HL-1





1 1 1 0 1 1 0 1$ED
1 0 1 0 1 0 1 0$AA


The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B can be used as a byte counter, and its contents are placed on the top half (A8 through A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to the CPU. The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory. Finally, the byte counter and register pair HL are decremented.

Condition Bits Affected

Sis unknown
Zis set if B-1=0, otherwise it is reset.
His unknown
P/Vis unknown
Nis set.
Cis not affected.


Register C contains $07, Register B contains $10, the HL register pair contains $1000, and byte $7B is available at the peripheral device mapped to I/O port address $07. Upon the execution of


memory location $1000 contains $7B, the HL register pair contains $0FFF, and Register B contains $0F.