(HL) <- (C), B <- B-1, HL <- HL+1
INIR
None
| b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | $ED |
| 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | $B2 |
The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B is used as a byte counter, and its contents are placed on the top half (A8 through A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to the CPU. The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory. Then register pair HL is incremented, the byte counter is decremented. If decrementing causes B to go to 0, the instruction is terminated. If B is not 0, the Program Counter is decremented by two and the instruction repeated. Interrupts are recognized and two refresh cycles execute after each data transfer.
Note: If B is set to 0 prior to instruction execution, 256 bytes of data are input.
| S | is unknown |
| Z | is set. |
| H | is unknown |
| P/V | is unknown |
| N | is set. |
| C | is not affected. |
Register C contains $07, Register B contains $03, the HL register pair contains $1000, and the following sequence of bytes is available at the peripheral device mapped to I/O port of address $07.
| $51 |
| $A9 |
| $03 |
Upon the execution of
INIR
the HL register pair contains $1003, Register B contains a 0, and the memory locations contain the following data:
| $1000 | $51 |
| $1001 | $A9 |
| $1002 | $03 |