JP cc,nn

Operation

IF cc true, PC <- nn

Mnemonic

JP

Operands

cc,nn

b7b6b5b4b3b2b1b0
1 1 cc 0 1 0
n
n

Note: The first operand in this assembled object code is the low-order byte of a two-byte address.

Description

If condition cc is true, the instruction loads operand nn to register pair Program Counter (PC), and the program continues with the instruction beginning at address nn. If condition cc is false, the Program Counter is incremented as usual, and the program continues with the next sequential instruction. Condition cc is programmed as one of eight statuses that correspond to condition bits in the Flag Register (Register F). These eight statuses are defined in the following table, which specifies the corresponding cc bit fields in the assembled object code.

ccHexConditionRelevant
Flag
000$C2Non-Zero (NZ)Z
001$CAZero (Z)Z
010$D2No Carry (NC)C
011$DACarry (C)C
100$E2Parity Odd (PO)P/V
101$EAParity Even (PE)P/V
110$F2Sign Positive (P)S
111$FASign Negative (M)S

Condition Bits Affected

None

Example

If the Carry flag (i.e., the C flag in F Register) is set and address $1520 contains $03, then upon the execution of

	JP	C,$1520

the Program Counter contains $1520 and, on the next machine cycle, the CPU fetches byte $03 from address $1520.