(C) <- (HL), B <- B-1, HL <- HL-1
OTDR
None
| b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | $ED |
| 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | $BB |
The contents of the HL register pair are placed on the address bus to select a location in memory. The byte contained in this memory location is temporarily stored in the CPU. Then, after the byte counter (B) is decremented, the contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B can be used as a byte counter, and its decremented value is placed on the top half (A8 through A15) of the address bus at this time. Next, the byte to be output is placed on the data bus and written to the selected peripheral device. Then, register pair HL is decremented and if the decremented B Register is not 0, the Program Counter (PC) is decremented by two and the instruction is repeated. If B has gone to 0, the instruction is terminated. Interrupts are recognized and two refresh cycles are executed after each data transfer.
When B is set to 0 prior to instruction execution, the instruction outputs 256 bytes of data.
| S | is unknown |
| Z | is set. |
| H | is unknown |
| P/V | is unknown |
| N | is set. |
| C | is not affected. |
Register C contains $07, Register B contains $03, the HL register pair contains $1000, and memory locations contain the following data.
| $0FFE | $51 |
| $0FFF | $A9 |
| $1000 | $03 |
Upon the execution of
OTDR
the HL register pair contain $0FFD, Register B contains a 0, and a group of bytes is written to the peripheral device mapped to I/O port address $07 in the following sequence:
| $03 |
| $A9 |
| $51 |