RLC (IY+d)

Operation

      n---------------m
n--m  | n----------m  |
|CY|<-T-|7<-------0|<-u
v--u    v----------u
           (IY+d)

Mnemonic

RLC

Operands

(IY+d)

b7b6b5b4b3b2b1b0
1 1 1 1 1 1 0 1$FD
1 1 0 0 1 0 1 1$CB
d
0 0 0 0 0 1 1 0$06

Description

The contents of the memory address specified by the sum of the contents of Index Register IY and the two’s-complement displacement integer, d, are rotated left 1 bit position. The contents of bit 7 are copied to the Carry flag and also to bit 0. Bit 0 is the least-significant bit.

Condition Bits Affected

Sis set if result is negative, otherwise it is reset.
Zis set if result is 0, otherwise it is reset.
His reset.
P/Vis set if parity even, otherwise it is reset
Nis reset.
Cis data from bit 7 of source register.

Example

Index Register IY contains $1000 and the contents of memory location $1002 are:

76543210
10001000

Upon the execution of

	RLC	(IY+$2)

memory location $1002 and the Carry flag now contain:

C76543210
100010001