SLL (IY+d)

Operation

n--m  n----------m
|CY|<-|7<-------0|<-- 0
v--u  v----------u
         (IY+d)

Mnemonic

SLL

Operands

(IY+d)

b7b6b5b4b3b2b1b0
1 1 1 1 1 1 0 1$FD
1 1 0 0 1 0 1 1$CB
d
0 0 1 1 0 1 1 0$36

Description

An arithmetic shift left 1 bit position is performed on the contents of the memory address specified by the sum of the contents of Index Register IY and the two's-complement displacement integer, d. Bit 0 is set and the contents of bit 7 are copied to the carry flag.

Condition Bits Affected

Sis set if result is negative, otherwise it is reset.
Zis set if result is 0, otherwise it is reset.
His reset.
P/Vis set if parity even, otherwise it is reset
Nis reset.
Cis data from bit 7.

Example

Index Register IY contains $1000 and the contents of memory location $1002 are:

76543210
10110001

Upon the execution of

	SLL	(IY+$2)

memory location $1002 and the Carry flag now contain:

C76543210
101100011