SLL r

Operation

n--m  n---------m
|CY|<-|7<------0|<-- 1
v--u  v---------u
           r

Mnemonic

SLL

Operands

r

b7b6b5b4b3b2b1b0
1 1 0 0 1 0 1 1$CB
0 0 1 1 0 r

Description

An arithmetic shift left 1 bit position is performed on the contents of register r. Bit 0 is set and the contents of bit 7 are copied to the carry flag. Bit 0 is the least-significant bit. In the assembled object code, operand r is specified as follows:

RegisterrHex
A111$37
B000$30
C001$31
D010$32
E011$33
H100$34
L101$35

Condition Bits Affected

Sis set if result is negative, otherwise it is reset.
Zis set if result is 0, otherwise it is reset.
His reset.
P/Vis set if parity even, otherwise it is reset
Nis reset.
Cis data from bit 7.

Example

Register L contains the following data:

76543210
10110001

Upon the execution of

	SLL	L

register L and the Carry Flag now contain:

C76543210
101100011