n----------m n--m
0 -->|7------->0|->|CY|
v----------u v--u
(HL)
SRL
(HL)
| b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | $CB |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | $3E |
The contents of the memory address specified by the contents of the register pair HL are shifted right 1 bit posistion. The contents of bit 0 are copied to the Carry flag, and bit 7 is reset.
| S | is set reset. |
| Z | is set if result is 0, otherwise it is reset. |
| H | is reset. |
| P/V | is set if parity even, otherwise it is reset |
| N | is reset. |
| C | is data from bit 0. |
The HL register pair contains $2828 and the contents of memory location $2828 are:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
Upon the execution of
SRL (HL)
memory location $2828 and the Carry flag now contain:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | C | |
|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |